In general, integrated circuit memory devices include a plurality of memory cells arranged in rows and columns that extend along a respective row direction and column direction. A specific memory cell is selected by a row address and a column address. The data of the selected memory cell moves to local input and output lines through a pair of bit lines.
When many memory cells are connected to a pair of bit lines, the parasitic capacitance may increase. Accordingly, the memory may operate more slowly, due to the large parasitic capacitance, as the number of memory cells connected to a pair of bit lines increases. Also, when all the cells of a memory device are in one block, multi-bit input and output may be difficult to perform. Therefore, the memory device may be divided into multiple banks. Each bank can independently input and output data. Such a structure is called a "stack bank" architecture.
FIG. 1 is a block diagram showing the input and output lines of a memory device having a conventional stack bank structure. Referring to FIG. 1, in the memory device having the stack bank structure, a bank has a structure like that of stacked bricks. Each bank has a row decoder, a sense amplifier, and a local column decoder. Global input and output lines GIO use a common data bus. The row decoder is selected by a row bank address and is activated by selecting the word line of the memory cell. The word line of the memory cell is arranged in the row direction. The local column decoder is operated by the output signals of a column bank address and a global column decoder. There is one local column decoder in every bank. The output signal lines of the global column decoder GCSL and the output signal of the local column decoder LCSLi are all arranged in the column direction. When the word line is selected by the row bank address and the row address, all the sense amplifiers of the selected banks operate. The data of the selected bank is amplified by the sense amplifier and moves to the local input and output lines in the row direction. The data moved to the LIO again moves to the global input and output lines GIO. The global input and output lines GIO are commonly connected to the memory banks and are arranged in the column direction.
FIG. 2 is a block diagram showing a faulty cell repairing circuit for the memory device of FIG. 1. In the faulty cell repairing circuit of FIG. 2, a normal switch is arranged between the data line DIOi of the memory cell and a local input and output line LIOi. A redundancy switch is arranged between a redundancy input and output line RIO and the local input and output line LIOi. All the normal switches are turned on in a normal operating mode. At this time, the redundancy switches are all turned off. Therefore, the data lines DIOi are respectively connected to the local input and output lines LIOi. For example, data can be input and output since DIO0 is connected to LIO0, DIO1 to LIO1, and DIOn-1 to LIOn-1.
However, when a cell is faulty, the normal switch of the related column is turned off and the redundancy switch is turned on. For example, when a faulty cell is generated in the column corresponding to the data line DIO1, a normal switch 205 connected to the data line DIO1 is turned off and a redundancy switch 207 is turned on. Therefore, the local input and output line LIO1 is disconnected from the data line DIO1 and connected to the redundancy input and output line RIO. The remaining data lines are connected to the respective local input and output lines and operate as in the normal operating mode.
Memory devices and faulty cell repairing circuits having the stack bank structure according to conventional technology may have problems. First, in a memory device having the conventional stack bank structure, the layout area may increase when the input and output lines increase. In particular, the local input and output lines LIO are assigned to each bank. A local column decoder exists in each bank. When increasing the input and output lines, the memory cell banks may be divided more or the number of local input and output lines output through the sense amplifier may increase. Also, the number of global input and output lines to which the respective local input and output lines are connected may increase. Therefore, the input and output lines may increase in the row and column directions of a memory chip.
Second, memory devices having the conventional stack bank structure may draw a large current. Since the local column decoder of each bank generally operates in a reading or writing mode, the current increases. Third, a load difference is generated based upon the different distances between the global input and output lines and the respective points of the local input and output lines. Accordingly, a time difference in outputting data from the respective columns to the global input and output lines may be generated, thus deteriorating the performance of the memory. Finally, in the faulty cell repairing circuit of FIG. 2, a plurality of redundancy switches are connected to the redundancy input and output line RIO. Therefore, the data may be input and output more slowly during the redundancy operation.